This invention relates to systems and methods for sensing memory cells in memory cell arrays.
In general, a memory system includes a plurality of memory elements that are arranged in an array of individually accessible cells. Many different memory systems are available for different applications. For example, volatile memories (e.g., dynamic random access memories), which require a continuous source of power to retain their contents, provide high storage capacity and versatile programming options for microprocessor-based applications. Nonvolatile memories (e.g., read only memories and programmable logic arrays), which do not require a continuous source of power to retain their contents, provide relatively lower storage capacity and limited programming options.
Nonvolatile memories typically store information in one of two ways. In particular, a nonvolatile memory may store a charge or may store a unique physical structure. A charge-storing nonvolatile memory uses a relatively small electrical current to store a charge at a memory element location. A structure-changing memory, on the other hand, typically uses a large electrical current to change the physical structure of a memory element (e.g., a fuse or a chalcogenide memory element). In both charge-storing and structure-changing nonvolatile memories, an access device (e.g., access transistor or an access diode) typically provides individual access to an associated memory element. During a read operation, all of the access devices in the memory array are turned off except the access device associated with the particular memory cell to be read. In the case of a diode-based memory system, the cumulative reverse bias current of the diodes corresponding to the non-sensed memory elements may significantly reduce the signal-to-noise ratio of the sensed response to the signal applied to the memory cell being read, making it difficult to accurately determine the memory state of the cell.
The invention features a novel memory cell reading scheme (systems and methods) that enables the state of a memory cell to be determined with greater accuracy.
In one aspect, the invention features a memory cell reading scheme in which a memory cell is addressed, an input signal is applied to the addressed memory cell over a range of values, and the state of the memory cell is read based upon a discontinuity in a sensed electrical response to the applied input signal values.
Embodiments of the invention may include one or more of the following features.
The state of the memory cell preferably is read based upon a discontinuity in the sensed electrical response over a range of applied input signal values encompassing a rail voltage value (e.g., within one or more diode drops of the rail voltage value).
The state of the memory cell may be read based upon a discontinuity in direction of the sensed electrical response. The state of the memory cell also may be read based upon a discontinuity in slope of the sensed electrical response. The state of the memory cell may be read based upon the presence or absence of a discontinuity in an electrical response to the applied input signal.
The state of the memory cell may be read multiple times within a read period. A noise immunity process may be applied to the multiple memory cell readings. In one embodiment, the noise immunity process comprises an integrate and dump process. In some embodiments, an electrical response to an applied row signal is sensed and an electrical response to an applied column signal is sensed. A common mode rejection noise immunity process may be applied to the sensed electrical responses to the applied row and column signals.
Among the advantages of the invention are the following.
The invention provides a memory cell reading approach that may be applied readily to diode-based memory systems. In general, the invention is relatively insensitive to noise. For example, the invention is relatively insensitive to noise caused by reverse bias leakage currents that are characteristic of diode-based memory systems. The invention also may be configured to provide a digital sense signal, which may be processed easily by digital processing equipment.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.